Fabless demise greatly exaggerated
Recent negative news flow suggesting the demise of the fabless semiconductor business model has been greatly exaggerated. There are some formidable challenges ahead, but we feel they will be mitigated by a combination of supply chain management, new EDA systems tools and a syndicated, collaborative group of well versed and connected VC investors.
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Fabless semiconductor companies represent one of the best IRRs for VC investors, as there are very few industry sectors that have double digit , ‘J curve’ type growth, as highlighted by this year’s VC investments in NemeriX, DiBcom, Innova Card, Dresden Silicon, On Demand Microelectronics, Frontier Silicon, Oxford Semiconductors, picoChip and Icera, to name just a few.
A well tested and tried business model
The establishment of independently owned semiconductor foundries in the late 1980s – such as TSMC and UMC in Taiwan, and Chartered Semiconductor in Singapore – has enabled the birth of a whole new set of fabless companies.
The fabless model has created billion dollar turnover companies such as Xilinx, Altera, Broadcom, ATI and Nvidia, followed by numerous other companies occupying high growth market niches, for which IDMs (integrated device manufacturers, who have their own semiconductor fabs) have no time or inclination to address. Fabless models have been well tested and tried, so the inherent investment risk of an unknown business model is greatly reduced. What has changed is the risk appetite of investors, which will be short-lived, as the risks mitigation plans come into play.
Fabless model decline does not match the numbers
At the recent Future Horizons (FH) International Fabless Forum, Chris Ryan, FH industry analyst, pointed out that the total fabless company revenue is forecast to grow by 20 percent, which is more than twice the growth of the overall semiconductor market. The fabless market growth has been consistently higher than the overall market in 2002, 2003, 2004 and now 2005.
The total fabless market will reach slightly short of the $40 billion mark, and will represent 17 percent of the overall semiconductor market in 2005, up from 15.6 percent in 2004. Ryan further added that the share held by the top 10 fabless companies declined from 53 percent to 49.3 percent, and that the fabless companies outside this top 10 are growing at 2.5 times the top 10 companies.
Although gross margins at fabless companies range from 43 percent to 48 percent, as opposed to the gross margin of 47 percent to 51 percent for IDMs, this is at the expense of far more capital outlay at IDMs compared to fabless companies. By any imagination, this does not paint a picture of a declining sector or ill health. The fabless model is so proven that some IDMs use it to supplement their internal fab capacity with the so called fab-lite model.
Fabless companies come in many flavours
Lumping all fabless companies into one set of business rules hides some major underlying differentiators and raison d’etre, Some fabless, especially start-ups, focus on a single set of emerging standards, such as WiMAX, UWB (ultra wide band) , Wi-Fi, ZigBee or Bluetooth. Their main calling card is that they are ahead of the curve in not only identifying a new market, but leveraging of new but unsettled sets of industry standard specifications.
Other sets of fabless companies address multi-market niches with innovative, novel and differentiated products, such as microcontrollers, DSP based platforms (hardware, application software and tools) and novel memory design or architecture.
Some fabless companies differentiate via novel mixed mode/RF, wireless design; others differentiate via software and tools support. Some, like in industrial or automotive, will use supplementary competence in terms of packaging, special test equipment or flexible inventory cycle.
New set of challenges will bring new solutions
Despite this, fabless companies face a whole new set of challenges in terms of rising design costs, technical challenges associated with low power and 90nm and 65nm geometries, manufacturing yield, time to market risks and not to forget the risk averse VC investment community, especially in Europe.
Mitigating the design costs and ownership risks
Rahul Sud of Silicon Capital, one of the panel members at the FH Fabless Forum, said of the challenges of 65nm designs: “In today’s designs 70 out of 100 designers in a chip project are verification engineers, i.e. they represent 70 percent of the costs. In future designs, verification will represent 90 percent of the costs”. Sud added that not getting the verification right not only means losing $10s of millions in sunk cost, but also missed marketing window opportunities.
“The main drivers of the 1990s capital intensive foundries will be transgressed by brain/intellectual intensity of thousands of engineers.”
Part of the solution in which he has direct experience is to consider working with design foundries which can muster a large pool of suitably qualified engineers at a reasonable cost and time, whether they are located in Romania, Russia, China or India. Effective management of this strategic design supply chain can help mitigate some of the rising costs.
The glue, which will holds the disparate designs team together and mitigates the design risks will come in the form of new EDA design and collaboration tools.
Design costs cannot be looked at in isolation: what matters is whether an end customer is getting their price/performance criteria, regardless of how design and manufacturing costs are allocated internally.
Programmable solution, part of the solution
For the consumer market, which is the mainstay of the current boom, component pricing is the key criteria: even a 2 to 5 cent cost savings per chip matters a lot. So the purveyors of programmable, off-the-shelf solutions should be careful in over-stating their flexibility. By its own nature, flexibility brings higher costs, as it has to carry excess baggage to suit different applications.
Having said that, there are a lot mid-volume markets where programmable solutions (structured ASICs, microcontrollers, DSPs) will satisfy the cost of ownership and time to market criteria. For exploring new applications and markets, programmable solutions are an ideal vehicle, but whether they can be successfully translated into a cheaper custom design for volume delivery and still catch the market window remains to be proved.
Execution risks
New EDA tools which enhance designer productivity, design for manufacturing (DFM) EDA tools, working closely with collaborative foundry partners, will overcome the challenge of sharing closely guarded proprietary foundry data. This will help mitigate not only design rule failures but also help achieve reasonable production yields.
This will provide a counterbalance to the disaggregating argument (used by IDMs, where such data are freely shared internally) as foundries cannot stay empty. They will share data via black boxes, so that effective design can be yielded. It is not in the foundries’ interest to produce bad yield product, as it will affect their own customers’ market, which in turn will affect them.
Those foundries that rely on existing fabless companies only, without supporting new ones, will miss out on new market opportunities as start-up companies tend to stick to the foundries where they have built working relationships and shared proprietary information.
Mitigating the management and market traction risks
The gene pool of managing successful fabless companies has been growing ever since the formation of independent foundries. The major issue is the location of those skills and their willingness to relocate to other parts of the world.
Given the right level of compensation and safety nets, managers can be recruited to help new start-ups get rapid market traction and supply chain enhancements. As Europe does not have as many fabless companies as they do in the USA and Taiwan, it is difficult to get a water flow of skills transfer within Europe; but this should not stop investors in recruiting suitably qualified candidates from abroad and when necessary from incumbent IDMs.
Paying extra for those skills that allow for flexible designs for future re-spins, or software fix, product migration or orbits into other market categories will produce handsome paybacks. More valued are managers who have experience and relationship with key OEMs and ODMs, and understanding how to switch on automatic resources, not only in terms of quantity but also quality from the supply chains in China and India.
As Rahul Sud pointed out, “The ability to motivate and manage global complexity will become a major differentiator.”
Cross border VCs and syndicates
It used to be that VCs would only invest in companies which were less than a two-hour drive from their office. The VC market is not only becoming more cross-country and global, but also becoming more specialized, as they cannot rely on general market knowledge and deal flow to provide the required IRRs in the future, without heavily investing in back office investment research.
For some VC funds, the challenges highlighted above may be too formidable and risky considering the total amounts required for fabless companies before they reach exit potential ($35 to $50 million).
Others VCs who have had successful fabless exits in the past see the new challenges as new opportunities. They will minimize their total outlay by forming cross border collaborative syndicates and bring complimentary OEM, ODM, national and global networks of supply chain and relationships. Only those syndicates, with the right relationships and networks will be able to take their fabless company from initial prototype all the way to a successful exit via IPO or M&A, and that would be reflected in the exit values.
TheChilli perspective
No doubt fabless companies will face new challenges and technology barriers as the industry moves to new geometries, but the industry will find creative technology solutions based around new EDA tools, innovative supply chain to minimize costs and design risks, backed by collaborative VC syndicates which will add value from their extended relationships and networks.
The fabless industry is still in its early formative years and there are vast numbers of niches in the medical diagnostics, biotechnology fluidics, pharmatronics, mechatronics, telemetry, automotive and transportation, health, and education, which have yet to be explored and discovered.
So the demise of the fabless semiconductor business model is highly exaggerated and premature. Whether the products are ASSP (application specific standard product) or programmable platforms/system on a chip, they still have to be manufactured in a fab, and the design/fabless/foundry platform is the most efficient so far. Even the IDMs are making good use of this model.
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